1. Field of the Invention
The present invention relates to data bus inversion for logic circuits, and more particularly to a method and apparatus for rapidly evaluating state changes for a group of data output bits for the purpose of inverting their state and indicating data bus inversion, such as according to x86 microprocessor protocol.
2. Description of the Related Art
The architecture of the X86 type microprocessors, such as those manufactured by the Intel Corporation, provides a technique for limiting the noise on the data bus. This technique, called data bus inversion, operates to invert the bus signals if a majority (i.e., more than half) of the bus signals would otherwise change state from one bus cycle to the next. Data bus inversion ensures that half or less of the output bus data signals change state during each cycle. The current x86 protocol features a 64-bit data bus D[63:0]# consisting of four 16-bit groups D[63:48]#, D[47:32]#, D[31:16]# and D[15:0]#. A group of data bus inversion (DBI) bits DBI[3:0]# indicates the polarity of each data group of the data bus. In particular, during every bus cycle, each DBI bit in the DBI[3:0]# signal group indicates the polarity of a corresponding 16-bit group of data bus signals. According to standard terminology, the ‘#’ symbol following a signal name implies that the signal is active low. Thus, if DBI[3:0]=‘HLHL’, then DBI[3:0]#=‘LHLH’ where ‘H’ denotes a High logic level and ‘L’ denotes a Low logic level. For the data signals D[63:0]#, however, the DBI[3:0]# signals are used to determine data bit polarity.
Logic within an x86 microprocessor is required to evaluate each of the 16-bit groups of data before the data is driven out to the external input/output (I/O) bus. To limit noise on the bus, if more than half of the signals within a signal group change state, then the signal group is driven out to the external bus in opposite polarity, and the state of the data bus signal group's corresponding DBI signal is set to indicate the selected polarity. Hence, a maximum of up to half of the data bits change state from one bus cycle to the next, thereby reducing noise caused by logic level switching. If all 16 bits in the data bus signal group change state on the next bus cycle, rather than toggling all 16 signals within the group, the signals are driven out in their previous logic state, and their corresponding DBI signal is toggled.
The prevailing technique for evaluating the changed state of groups of bits is a combinatorial digital adder. Each of the 16 bits in a group are provided to the adder and a cumulative sum is generated. This technique consumes valuable time potentially resulting in an additional clock delay to complete. It is desired to achieve the noise-reducing benefits of data bus inversion without adding clock delays on the external data bus.